The present invention relates to a semiconductor device, further, to a serial communication technology therein, and to a technology effective when applied, for example, to a microcomputer.
A microcomputer (also called a data processing device or microprocessor) as an example of a semiconductor device is widely used for the purpose of equipment control. An SCI (Serial Communication Interface) for performing serial data communication is incorporated in a microcomputer. Data is transmitted or received bit by bit via the SCI. The speed of transmitting or receiving one bit is called a bit rate. An SCI has an asynchronous communication mode for which a bit rate is predetermined between the transmit side and the receive side. The difference or error between the bit rate on the transmit side and that of the receive side needs to be small. Further, there are specific speeds that are generally used for a bit rate, such as 460.4 kbps, for example.
Inside a microcomputer, one bit period is measured, based on the operation clock of the microcomputer or the SCI. An operation clock of a microcomputer also has a specific frequency generally used, such as 10.667 MHz, for example.
In a case of an asynchronous communication method, as it is necessary to detect the communication state only by data, a basic clock that is 8 times or 16 times of a bit rate is used. The basic clock is formed based on the operation clock of a microcomputer or an SCI. With reference to the basic clock, a start is detected, and then, according to a predetermined bit rate, subsequent data is sampled at the center of the bit. For the measurement of the above-described one bit period, the basic clock is measured, and further, 8 or 16 basic clocks are measured.
Japanese Patent Laid-Open No. 2001-168853 (Patent Document 1) and Japanese Patent Laid-Open No. 1999-149325 (Patent Document 2) are examples of documents describing a serial data communication technology.    Patent Document 1 describes a technology for eliminating failure to receive data, even when a data transfer speed significantly changes.    Patent Document 2 describes a technology for realizing a receive-serial-clock generation circuit that enables, even when a frequency that is N (N is a natural number.) times of a targeted serial transfer speed cannot be provided as an input clock, data reception at this transfer speed.